A typical data processor has a microsequencer and an execution unit. Within the execution unit various dam operations are performed. The execution unit typically comprises an arithmetic unit, registers, communication buses, and a shifter. The microsequencer is usually either `hardwired`, i.e. designed using combinatorial logic gates, or `microcoded`, i.e. designed using a programmable memory. A microcode designed microsequencer has the advantage that the microsequencer architecture is more simple and straightforward than a hardwired design, and the microsequences can be easily modified by reprogramming the memory. Microcode thus becomes a collection of microprogram routines which implement the user-visible, macroinstruction set of the data processor. In a microcode design the memory is referred to as the microstore, and is often implemented as read only memory (ROM), or as read/write, random access memory (RAM).
There are generally two classes of information contained in a typical microprogram control store ROM word. The first class is actual control information, which controls such things as an arithmetic logic unit (ALU), a Shifter, and register transfer operations; the second class of information in a microprogram control store is commonly referred to as Next Micro Address (NMA) information. NMA information is usually an address which specifies the next access into the control store ROM. Therefore, when a microinstruction is fetched from the control store, the control information is used to control the ALU, Shifter, register transfers, etc., and the NMA information tells the microsequencer where to get the next microinstruction.
In U.S. Pat. No. 4,307,445 by Tredennick et al. entitled "Microprogrammed Control Apparatus Having A Two-Level Control Store For Data Processor" and assigned to the assignee herein, a dual ROM control store structure is described in which one ROM contains control information and a second ROM contains NMA information. Both ROMs have their own address decoders and these decoders are configured in such a way so as to "share" a single control ROM word with multiple NMA ROM words.
Referring to FIG. 1, a known split level microstore 10 for use in a data processor is shown. An NMA-ROM 17 and a control ROM 18 are illustrated wherein each ROM contains three words. NMA-ROM 17 contains words 11, 12 and 13 having address contents respectively labeled addresses "B", "C" and "A". Control ROM 18 contains words 14, 15 and 16 having control operand contents respectively labeled "X", "X" and "Y". A Next MicroAddress (NMA) is connected to each of a control ROM address decoder 19 and an NMA-ROM address decoder 20. Address decoder 20 is connected to each of words 11, 12 and 13, and respectively provides addresses labeled A', B' and C'. Address decoder 19 is connected to each of words 14, 15 and 16, and also respectively provides addresses A', B' and C'. In the illustrated form, address A' is formed as a portion of the address contents A. Similarly, address B' is formed from a portion of address contents B and address C' is formed from a portion of address contents C.
When address A' is issued by each of decoders 19 and 20, each of ROMs 17 and 18 is respectively accessed at words 11 and 14. In response thereto, control information labeled `X` is outputted by control ROM 18. A next microaddress (NMA) labeled B' is derived by using the contents of word 11 of NMA-ROM 17 when addressed by address A'. Information stored within control ROM 18 essentially controls the registers, ALU, etc. of a data processor according to the bit pattern of the control information X and causes the next microinstruction at address B' to be retrieved. When the next microinstruction is fetched from each of words 12 and 15 by using address B', the microinstruction also is used to control the registers, ALU, etc. of the data processor according to the bit pattern of the control information X. A next microaddress (NMA) labeled C' is derived by using the contents labeled C of word 12 of NMA-ROM 17 when addressed by address B'. When the next microinstruction is fetched from each of words 13 and 16 by using address C', the microinstruction also is used to control the register, ALU, etc. of the data processor according to a bit pattern of control information labeled "Y". The NMA-ROM 17 contains within word 13 an address A' which is the address of the next microinstruction to be executed. Note that there are two control ROM words, words 14 and 15, which contain the bit pattern of the control information X.
Shown in FIG. 2 is split level microstore 10' which is a known modification of split level microstore 10 of FIG. 1 wherein words 14 and 15 are combined into one word and respond to either address A' or address B'. For convenience of comparison, comparable elements of FIG. 2 are numbered the same as in FIG. 1. In the modified form, a control ROM 18' has only two words, words 21 and 22. Decoder 19 is connected to words 21 and 22 wherein either address A' or address B' may address the contents of word 21 which is control information X. Address C' addresses the contents of word 22 which is control information Y.
By combining words 14 and 15 of FIG. 1, control ROM 18' of microstore 10' is reduced in size substantially by one-third. Using this scheme, the control information for addresses A' and B' is still the bit pattern of control information X. Also, the NMA information for each of addresses A', B' and C' is still unique. Word 21 of control ROM 18' is addressed along with either word 11 or word 12 of NMA ROM 17.
There are two important system conditions which must exist to allow the illustrated sharing to exist. First, two or more words in control ROM 18' have to contain identical contents; and second, the addresses for those words which are identical have to be assigned such that an address decoder can easily respond to multiple addresses. For example, if two identical control words are assigned the binary addresses 1000.sub.2 and 1001.sub.2, the words may be collapsed into one word whose address decoder is 100X.sub.2 (`X` indicates a `do not care` condition, where either a 1 or 0 will match). Therefore, the address decoder for this location only needs to decode the three upper bits.
An added complication is the fact that address restrictions may apply to various word placements due to circuit implementation size and speed tradeoffs. For example, when implementing a conditional microbranch, it is often beneficial to restrict both branch paths' addresses such that they differ by only a specific bit(s) as opposed to fully specifying both addresses. An important fact is that it is desirable to have as many control words appear identical as possible because address restrictions might preclude many of the control words from being combine shared. In other words, addresses may not readily be assignable in a manner so that two control words can be shared. Therefore, it is typically required to have more than two control words with identical contents so that alternate address assignments can be made.